Cellular and wireless communication technologies have seen explosive growth over the past several years. This growth has been fueled by better communications, hardware, larger networks, and more reliable protocols. Wireless service providers are now able to offer their customers an ever-expanding array of features and services, and provide users with unprecedented levels of access to information, resources, and communications. To keep pace with these service enhancements, mobile electronic devices (e.g., cellular phones, tablets, laptops, etc.) have become more powerful and complex than ever. For example, mobile electronic devices now commonly include system-on-chips (SoCs) and/or multiple microprocessor cores embedded on a single substrate, allowing mobile device users to execute complex and power intensive software applications on their mobile devices. As a result, a mobile device's battery life and power consumption characteristics are becoming ever more important considerations for consumers of mobile devices.
Methods for improving the battery life of multiprocessor devices generally involve reducing the amount of energy consumed by reducing the voltage applied to the processors/cores when they are idle or lightly loaded. Reducing the voltage applied to processors/core necessarily involves reducing the frequency at which the processors operate. Such reductions in frequency and voltage may be accomplished by scaling the voltage/frequency using dynamic clock and voltage/frequency scaling (DCVS) schemes/processes.
Generally, DCVS schemes/processes monitor the proportion of the time that the processor core is idle compared to the time it is busy to determine how the frequency and voltage should be adjusted to provide power-efficient operation. For example, the busy and idle periods may be reviewed, and a decision may be made regarding the most energy efficient performance of the processor, in real time or “on the fly.” However, existing DCVS solutions for multicore processors require that each processing core include a DCVS module/process and/or adjust the processor's frequency/voltage independent of other cores. Conventional DCVS solutions exhibit a number of performance problems, and implementing an effective DCVS method that correctly scales frequency/voltage for each core of multicore processor system is an important and challenging design criterion.